Symbolic Analysis and Reduction of VLSI Circuits

Symbolic analysis is an intriguing topic in VLSI designs.

The analysis methods are crucial for the applications to the parasitic reduction and analog circuit evaluation. However, analyzing circuits symbolically remains a challenging research issue. Therefore, in this book, we survey the recent results as the progress of on-going works rather than as the solution of the field.

For parasitic reduction, we approximate a huge amount of electrical parameters into a simplified RLC network. This reduction allows us to handle very large integrated circuits with given memory capacity and CPU time. A symbolic analysis approach reduces the circuit according to the network topology. Thus, the designer can maintain the meaning of the original network and perform the analysis hierarchically.

For analog circuit designs, symbolic analysis provides the relation between the tunable parameters and the characteristics of the circuit. The analysis allows us to optimize the circuit behavior.