Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness, and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. This book presents the state of the art in defect-oriented testing from both a theoretical and practical point of view. It offers step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices, which enables deeper understanding of concepts. The progression developed in this book is essential to understand new test methodologies, algorithms, and industrial practices. Without this insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage.

Design, Test, Quality and Reliability, product engineering professionals new to the field, graduate students and professionals in Electrical Engineering, and design and test managers